Static random access memory (SRAM) bitcells are arranged into rows and columns. Each row is accessed by a corresponding word line. The columns each have a corresponding bit line pair including a true bit line and a complement bit line. Each bitcell thus lies at an intersection of a word line and a bit line pair. When a word line is asserted, each bitcell in the corresponding row is coupled to the bit line pair for the bitcell's column.
In a write operation, a write driver discharges one of the bit lines in the column for an accessed memory cell while the corresponding word line is asserted. Prior to the write operation, all the bit line pairs are charged to a power supply voltage VDD. The write driver then discharges to ground either the true bit line or the complement bit line in the accessed column depending upon the binary value to be written to the corresponding bitcell.
To improve density, it is conventional for a set of columns to be multiplexed to a given write driver. For example, a conventional write driver includes a write bit gdin<0> and another for bit gdin<1>. Each write driver comprises a pair of inverters. A true bit line inverter in the pair drives the accessed true bit line by inverting the corresponding gdin write bit. A complement bit line inverter drives the accessed complement bit line by inverting the corresponding complement bit gdin_n.
In this example, there are eight columns being multiplexed. A selected one of columns 0 through Column 3 is driven by the write driver for write bit gdin<0> depending upon a set of write multiplexer bits wm<0> through wm<3>. In this case, wm<0> is asserted true while wm<1> through wm<3> are low. Thus, only column 0 is driven by the write driver in this particular write operation.
One word line from a set of word lines WL<0> through WL<n> is asserted by the same timing path used for a read operation. This common timing means that the word line will be asserted well before the write driver can discharge the appropriate bit line in the accessed column (Col. 0 being the accessed column in this example).
Since the word line is asserted during the write operation while the write driver is attempting to discharge a bit line, an unintended partial read operation occurs in the accessed bitcell depending upon its binary content. For example, suppose the write driver is attempting to discharge the true bit line in Col. 0 but that the accessed memory cell is storing a complementary binary state. The accessed memory cell will thus partially discharge the complement bit line while the write driver is discharging the true bit line. The complement situation may occur when the write driver is discharging the complement bit line but the accessed bit line is discharging the true bit line. In both cases, the unintended partial read operation undesirably lengthens the write time requirement and lowers write robustness. This delay is exacerbated in modern high-density architectures such as in a FinFET process node in which negative bit line boost techniques are employed.
In addition, the bitcells in the unselected columns across the accessed row will also perform such a partial unintended read operation, which undesirably wastes power. This power dissipation is increased as the column mux factor for the write driver is increased (e.g., in a 16:1 column muxing, 15 columns will droop one of their bit lines depending upon the binary content in the corresponding bitcells).
Accordingly, there is a need in the art for improved memory architectures that reduce power consumption and increase speed for write operations.